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Full text not available from this repository. (Request a copy)Abstract
Application-driven computers for Lattice Gauge Theory simulations have often been based on system-on-chip designs, but the development costs can be prohibitive for academic project budgets. An alternative approach uses compute nodes based on a commercial processor tightly coupled to a custom-designed network processor. Preliminary analysis shows that this solution offers good performance, but it also entails several challenges, including those arising from the processor's multicore structure and from implementing the network processor on a field-programmable gate array.
| Item Type: | Article |
|---|---|
| Uncontrolled Keywords: | ; |
| Subjects: | 500 Science > 530 Physics |
| Divisions: | Physics > Institute of Theroretical Physics > Chair Professor Braun > Group Tilo Wettig Physics > Institute of Theroretical Physics > Chair Professor Schäfer > Group Andreas Schäfer |
| Depositing User: | Dr. Gernot Deinzer |
| Date Deposited: | 19 Oct 2020 08:57 |
| Last Modified: | 19 Oct 2020 08:57 |
| URI: | https://pred.uni-regensburg.de/id/eprint/30083 |
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